This invention relates generally to semiconductor structures and manufacturing methods and more particularly to short channel metal-oxide-semiconductor (MOS) field-effect transistor structures and manufacturing methods.
As is known in the art, high performance MOS field-effect transistors generally require channel lengths below 3 .mu.m and even as short as 0.5 to 1.0 .mu.m. It is very difficult to obtain these small dimensions with present photolithographic techniques. This difficulty has led to the development of several types of transistors having channel lengths defined by means other than photolithography. One such device is generally referred to as a D-MOS transistor where two diffusions of dopants of opposite type conductivity are driven to different depths in a silicon substrate through one, noncritical mask opening, resulting in a channel length equal to the difference in the depth of the electrical junctions formed. Here, however, since the doping concentration varies along the channel, the "turn-on" voltage, which is a function of doping, is critically dependent on the location in the channel and the concentration at which the two diffusion profiles intersect. In practice, therefore, the "turn-on", or threshold voltage, will exhibit relatively large fluctuations because of the difficulty to control the two diffusions.
Other types of transistors wherein channel width is controlled by means other than photolithography are so-called "V-MOS" transistors and "D-V-MOS" transistors. With a V-MOS transistor the channel length is generally defined by the up-diffusion of boron from an n-type substrate into a p-type epitaxial layer formed on such substrate, in combination with a V-shaped groove etched through the epitaxial layer, down into the substrate. In the D-V-MOS transistor the channel is generally defined by an implant of boron from the top surface, through the n+ layer forming the source and drain, and again the intersection of the implanted zone with the walls of a V-shaped groove.